1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, to a semiconductor device in which an offset area is formed between an N.sup.+ active region and a P.sup.+ active region or between an N.sup.+ gate and a P.sup.+ gate in order to prevent unreliable silicidation caused by an increased dopant concentration, and a method of fabricating the same.
2. Description of the Related Art
Along with development of semiconductor devices towards high integration, high performance, and low voltage operation, a low-resistance gate and a new metalization technique for metal interconnection are required to reduce the gate length of a transistor and a memory cell through formation of fine patterns and improve device characteristics. The thickness of a gate insulating layer becomes smaller to increase a channel current in a transistor and a memory cell for low voltage operation. Further, in order to prevent short channel effect caused by the decrease in the gate length of a transistor and ensure a margin against punchthrough, the junction depth of source/drain regions should be small and the parasitic resistance, that is, surface resistance and contact resistance of the source/drain regions, should be reduced.
Under these circumstances, a self-aligned silicide (salicide) process is used as a new metalization technique, in which a silicide is formed on the surfaces of a gate and source/drain regions in order to reduce the resistivity of the gate and the sheet and contact resistance of the source/drain regions. The salicide process refers to selective formation of a silicide such as titanium silicide (TiSix) on a gate electrode and source/drain regions. Such a silicide is receiving considerable attention as a new metalization material because of (1) low resistance like a metal; (2) stable characteristics at high temperature; (3) easy pattern formation in a silicon layer or a polysilicon layer; (4) excellent mechanical stability such as good adherence and low stress; (5) unwillingness to react with a final metal layer; (6) low contact resistance; and (7) no contamination in wafer using equipment.
Such suicides include titanium silicide (TiSi.sub.2), cobalt silicide (CoSi.sub.2), and tantalum silicide (TaSi.sub.2). Among them, titanium silicide is widely used in that it is stably formed because it allows an interstitial native oxide film between the titanium silicide and a polysilicon layer to be dissolved, exhibits an excellent thermal stability and a low resistance, and can be selectively formed between a gate and source/drain regions. However, a problem with formation of the titanium silicide is that overgrown titanium silicide remains along the surface of spacers formed on the sidewalls of the gate, resulting in an electrical short between the gate and the source/drain regions. Also, discontinuity of the titanium silicide may take place during a subsequent high-temperature thermal treatment.
FIGS. 1 to 4 are sectional views sequentially illustrating a method of fabricating a semiconductor device, here confined to a P-well region, with use of a conventional salicide process.
Referring to FIG. 1, an N-well (not seen) is formed by ion-implanting an N-type dopant into the surface of an N-or P-semiconductor substrate 10 by photolithography and ion-implantation and diffusing the N-type dopant to an intended depth by high-temperature thermal treatment. Then, a P-well 11 is formed by ion-implanting a P-type dopant into the surface of the substrate 10 except for the N-well by photolithography and ion-implantation and diffusing the P-type dopant by high-temperature thermal treatment. The N-well and the P-well function to electrically isolate a PMOS transistor from an NMOS transistor on the substrate of a CMOS (Complementary Metal Oxide Semiconductor) device.
Following definition of an active region on the substrate 10 by forming a field oxide film (not seen) in a general device isolation process, a gate insulating layer (not seen) and a gate (not seen) for a transistor are sequentially formed on the surface of the substrate 10. Then, areas for forming source/drain regions of the NMOS transistor therein are opened on the P-well 11 by photolithography, and an N-type dopant is ion-irnplanted at ahigh dose, for example, at or above a dose of 1E15 ions/cm.sup.2, thereby forming an N.sup.+ active region 12. Thereafter, a P.sup.+ active region 14 is formed by opening a well contact forming area on the P-well 11 by photolithography and then ion-implanting a P-type dopant at a high dose, for example, at or above a dose of 1E15 ions/cm.sup.2. Here, the N.sup.+ active region 12 overlaps with the P.sup.+ active region 14 in a specific area 16 of the P-well 11 having both the N.sup.+ and P.sup.+ dopants ion-implanted due to misalignment involved in photolithography for forming the N.sup.+ and P.sup.+ active regions 12 and 14. Therefore, dopant concentration partially increases in the overlap area 16.
Though not seen, a P.sup.+ active region and an N.sup.+ active region are formed in an N-well region, to be provided as source/drain regions and a well contact for a PMOS transistor, respectively. Here, an overlap area is also formed between the N.sup.+ and P.sup.+ active regions in the N-well region, with both the N.sup.+ and P.sup.+ dopants ion-implanted therein.
Referring to FIG. 2, a silicide forming metal layer, preferably, a titanium (Ti) layer 18 is deposited on the resultant structure having the N.sup.+ and P.sup.+ active regions 12 and 14 formed thereon. Then, a titanium nitride (TiN) layer 20 is formed on the titanium layer 18 to prevent oxygen contamination and dopant loss during subsequent silicidation.
Referring to FIG. 3, silicidation is caused to take place in an area where titanium contacts silicon by RTA (Rapid Thermal Annealing) or high-temperature thermal treatment using a furnace. Thus, a titanium silicide (TiSi.sub.2) layer 22 is formed on the surfaces of the exposed gate and N.sup.+ and P.sup.+ active regions 12 and 14. An increase in the dopant concentration of the overlap area 16 between the N.sup.+ and P.sup.+ active regions 12 and 14 suppresses formation of a titanium silicide and leaves unreacted titanium 18a, thereby increasing the sheet resistance of the N.sup.+ and P.sup.+ active regions 12 and 14. It has been reported that this is attributed to segregation or accumulation of dopants contained in silicon in excess of their solid solubility limits at the interface and the resulting prevention of silicon diffision. The phenomenon is observed to be more serious with arsenic (As) than with phosphorous (P).
Referring to FIG. 4, the titanium nitride layer 20 and the unreacted nitride 18a are selectively removed with use of an etchant which does not damage the titanium silicide layer 22, the silicon substrate 10, and the gate insulating layer. However, no silicidation takes place or the silicide layer is broken (see area "A") in the overlap area 16 having a partially increased dopant concentration on the surface of the silicon substrate 10.
Meanwhile, an N.sup.+ polysilicon layer doped with POCL.sub.3 is used as a gate in both an NMOS transistor and a PMOS transistor of a general CMOS device. The NMOS transistor having the N.sup.+ polysilicon gate acts in a surface channel mode, while the PMOS transistor having the N.sup.+ polysilicon gate acts in a buried channel mode.
There is no problem with use of the N.sup.+ polysilicon gate both for the NMOS and PMOS transistors in a device having a 0.3 .mu.m or longer effective channel length. However, short channel effect emerges as a problem with a 0.2 .mu.m or longer gate length required for a device of 1 or more giga bytes, especially a PMOS transistor operated in the buried channel mode. That is, because a drain voltage has a great influence on a channel in a device operated in the buried channel mode, the device is more susceptible to the short channel effect than a device operated in a surface channel mode.
Accordingly, studies have been conducted on a method of fabricating a CMOS device having a dual gate structure of an N.sup.+ gate for an NMOS transistor and a P.sup.+ gate for a PMOS transistor.
FIG. 5 is a plan view of a conventional semiconductor device employing a dual gate structure. Here, reference numeral 52 denotes an N.sup.+ gate, reference numeral 54 denotes a P.sup.+ gate, reference numeral 56 denotes an N.sup.+ active region, and reference numeral 58 denotes a P.sup.+ active region.
Referring to FIG. 5, after a conductive layer is formed on a semiconductor substrate (not seen), the N.sup.+ gate 52 is formed by ion-implanting an N.sup.+ dopant into an NMOS transistor forming area by photolithography and ion-implantation. Then, the P.sup.+ gate 54 is formed by implanting a P.sup.+ dopant into a PMOS transistor forming area by photolithography and ion-implantation. Here, since the N.sup.+ gate 52 is in contact with the P.sup.+ gate 54, a threshold voltage may shift due to inter-diffusion between the N.sup.+ and P.sup.+ dopants during subsequent thermal treatment. In addition, misalignment involved in photolithography for forming the N.sup.+ and P.sup.+ gates 52 and 54 may lead to existence of an area having both the N.sup.+ and P.sup.+ dopants ion-implanted therein. Therefore, a dopant concentration increases in this area, which impedes reliable silicidation, damages a silicide layer, and thus markedly increases the sheet resistance of the gates.
FIGS. 6A and 6B are graphs of the thickness and sheet resistance, respectively, of a titanium silicide with respect to the dose of a dopant in polysilicon at 600.degree. C. Here, .smallcircle. represents use of arsenic as a dopant, and .quadrature. represents use of phosphorous as a dopant.
From FIGS. 6A and 6B, it is noted that with the increase in the dopant dose of a polysilicon layer, dopants contained in silicon in excess of their solid solubility limits are segregated or piled up at the interface, thereby blocking diffusion of silicon. Thus, a titanium silicide is not reliably formed and its sheet resistance is increased. This phenomenon is observed to be more serious with arsenic than with phosphorous.